asahi kasei [AKD4353] 00/04 - 1 - general description the AKD4353 is an evaluation board for ak4353, 96khz 24bit d/a converter with dit. the AKD4353 has a digital interface with akms wave generator using rom data and akms a/d converter evaluation boards. therefore, it is easy to evaluate the ak4353. n ordering guide AKD4353 --- evaluation board for ak4353 (cable for connecting with printer port of ibm-at compatible pc and control software are packed with this.) function on-board clock generator compatible with 2 types of interface - direct interface with akms a/d converter evaluation boards and direct interface with akms signal generator(akd43xx) by 10pin header - on-board cs8414 as dir which accepts optical input bnc connector for external clock input 10pin header for serial control interface on-board mute circuit for analog output optical output for tx output ak4353 2.7 ~ 5.5v gnd lch cs8414 (dir) clock generator opt out rom or a/d 10pin header divider opt in rch external clock mcko mcki control 10pin header mute dzf figure 1. AKD4353 block diagram * circuit diagram and pcb layout are attached at the end of this manual. evaluation board rev.a for ak4353 AKD4353
asahi kasei [AKD4353] 00/04 - 2 - n external analog circuit j1(aoutl) and j2(aoutr) are used. the analog output signal range is nominally 3.1vpp@5v. it is proportional to avdd (vout=0.62xavdd). n operation sequence 1) set up the power supply lines. [avdd] (red) = 2.7 ~ 5.5v : for avdd of ak4353 [3v] (orange) = 2.7 ~ 5.5v : for dvdd of ak4353 [5v] (red) = 3.4 ~ 5.5v : for logic [agnd] (black)= 0v : for analog ground (including avss and dvss of ak4353) [dgnd] (black)= 0v : for logic ground each supply line should be distributed from the power supply unit. 2) set up the evaluation mode, jumper pins and dip switches. (see the followings.) 3) power on. the ak4353 should be reset once bringing sw1(-pd) l upon power-up. 4) connect port2 with pc. connect port2 with printer port (parallel port) of ibm-at compatible pc by 10-line flat cable packed with the AKD4353. take care of the direction of connector. there is a mark at 1pin. the direction of port2 is as the following figure. port2 ctrl 1 -cs scl/cclk sda/cdti sda(ack) 2 9 10 5) set up the software. use the software named AKD4353 control program packed with the AKD4353. n evaluation mode 1) using a/d converted data port3 (adc/rom) is used to interface with various akms a/d converter evaluation boards. in case of using external clock through a bnc connector (j4), select bnc on jp14 (clk) and short jp15 (xte). jp12 dir_data jp14 clk jp6 lrck dir adc dir bnc xtl jp7 bick dir adc jp13 dir vd gnd jp15 xte
asahi kasei [AKD4353] 00/04 - 3 - 2) ideal sine wave generated by rom data digital signals generated by akd43xx are used. port3 (adc/rom) is used to interface with ak43xx. master clock is sent from AKD4353 to akd43xx and lrck, bick, sdti are supplied from akd43xx to AKD4353. in case of using external clock through a bnc connector (j4), select bnc on jp14 (clk) and short jp15 (xte). jp12 dir_data jp14 clk jp6 lrck dir adc dir bnc xtl jp7 bick dir adc jp13 dir vd gnd jp15 xte 3) dir(cs8414) port4 (torx174) is used for the evaluation using such as test disk. the dir generates mcki, bick, lrck, sdti from the received data through optical connector. in this case, the ext bit of ak4353 should be 1 (external clock mode). select rca or opt on jp16 (rca/opt) in case of using rca connector (j3) or optical connector (port4: torx174). jp12 dir_data jp14 clk jp6 lrck dir adc dir bnc xtl jp7 bick dir adc jp13 dir vd gnd jp15 xte n clock (mclk,bick,lrck) set up in case of using evaluation mode 1), jp9,10 and 17 should be set up as follows. they need no care for other evaluation mode. mclk jp9 (x_mclk) jp10 (x_lrck) bick jp17 (x_bick) 128fs x1 x1/128 32fs 64fs 128fs x1/4 x1/2 x1 256fs x1 x1/256 32fs 64fs 128fs x1/8 x1/4 x1/2 default 512fs x2 x1/256 32fs 64fs 128fs x1/8 x1/4 x1/2 1024fs x4 x1/256 32fs 64fs 128fs x1/8 x1/4 x1/2 table 1. clock set up
asahi kasei [AKD4353] 00/04 - 4 - n dip switch (sw2) set up no.1 to 5 set the mode of ak4353 and no.6 to 8 set the mode of cs8414. no. pin off on 1 cad1 2 cad0 chip address (2bit) 3 i2c 3-wire serial i2c bus 4 ttl cmos level ttl level 5 tst - always on 6m2 7m1 8m0 digital interface format of cs8414 (see table 3.) (note) table 2. dip switch set-up (note: m2-0 should be selected at only evaluation mode 3. in other mode, these should be off.) mode format m2 m1 m0 jp9 dif2 dif1 dif0 0 16bit, lsb justified 1 0 1 thr 0 0 0 1 18bit, lsb justified 1 1 0 thr 0 0 1 2 20bit, lsb justified ----010 3 24bit, lsb justified ----011 4 24bit, msb justified 0 0 0 inv 1 0 0 5 i2s 010thr101 table 3. digital interface format set-up (note: 1=on, 0=off. dif2-0 should be selected by serial control. cs8414 does not correspond to 20/24bit lsb justified format.) n serial control mode the ak4353 can be controlled via the printer port (parallel port) of ibm-at compatible pc. connect port2 (ctrl) with pc by 10-line flat cable packed with the AKD4353. there are two modes: 3-wire serial & i2c bus. jp4 should be shorted at 3-wire serial control mode. chip address can be selected by sw2(mode)-no.1(cad1) and no.2(cad0). n other jumper pins set up [jp1](gnd): analog ground and digital ground open: separated short: common (the connector dgnd can be open.) [jp2](5v-3v): dvdd of ak4353 and power supply to logic open: independent short: same (the connector 3v should be open.)
asahi kasei [AKD4353] 00/04 - 5 - [jp3](dvdd): dvdd of ak4353 3v: independent of avdd avdd: same as avdd (the connector 3v can be open.) [jp5](dzf): mute circuit on: used (analog output is muted when dzf=h.) off: not used [jp11](sdti): sdti of ak4353 data: data is input gnd: 0 data is input n the function of the toggle sw (sw1) upper-side is h and lower-side is l. [sw1] (-pd): resets the ak4353. keep h during normal operation. n the indication content for led [led1] (verf): monitors verf pin of the cs8414. led turns on when some error has occurred to cs8414. [led2] (prem): indicates whether the input data is pre-emphasis or not. led turns on when the data is pre-emphasised.
asahi kasei [AKD4353] 00/04 - 6 - measurement results [measurement condition] measurement unit : rohde & schwarz, upd04 mclk : 256fs bick : 64fs fs : 44.1khz, 96khz bw : 20hz ~ 20khz (fs=44.1khz), 20hz ~ 40khz (fs=96khz) bit : 24bit power supply : avdd=dvdd=5v, 3v interface : dir (fs=44.1khz), serial multiplex (fs=96khz) temperature : room fs=44.1khz parameter input signal measurement filter 5v 3v s/(n+d) 1khz, 0db 20klpf 97.0db 93.6db 20klpf 99.0db 94.6db dr 1khz, -60db 20klpf, a-weighted 102.3db 97.9db 20klpf 99.0db 94.6db s/n no signal 20klpf, a-weighted 102.3db 97.9db fs=96khz parameter input signal measurement filter 5v 3v s/(n+d) 1khz, 0db 40klpf 92.5db 90.8db 40klpf 97.0db 92.6db dr 1khz, -60db 20klpf, a-weighted 101.5db 97.1db 40klpf 97.0db 92.6db s/n no signal 20klpf, a-weighted 101.5db 97.1db [measurement condition] measurement unit : audio precision, system two, cascade mclk : 256fs bick : 64fs fs : 44.1khz, 96khz bw : 10hz ~ 20khz (fs=44.1khz), 10hz ~ 40khz (fs=96khz) bit : 24bit power supply : avdd=dvdd=5v, 3v interface : dir temperature : room fs=44.1khz parameter input signal measurement filter 5v 3v s/(n+d) 1khz, 0db 20klpf 97.4db 93.8db 20klpf 98.8db 94.3db dr 1khz, -60db 22klpf, a-weighted 101.6db 97.3db 20klpf 98.6db 94.3db s/n no signal 22klpf, a-weighted 101.8db 97.3db fs=96khz parameter input signal measurement filter 5v 3v s/(n+d) 1khz, 0db 40klpf 94.5db 91.5db 40klpf 96.9db 92.2db dr 1khz, -60db 22klpf, a-weighted 101.9db 97.3db 40klpf 96.8db 92.2db s/n no signal 22klpf, a-weighted 101.9db 97.3db
asahi kasei [AKD4353] 00/04 - 7 - n plots [measurement condition] measurement unit : audio precision, system two mclk : 256fs bick : 64fs fs : 44.1khz, 96khz bit : 24bit power supply : avdd=dvdd=5v interface : dir temperature : room [contents] 1. fs=44.1khz figure 1-1. thd+n vs. input level figure 1-2. thd+n vs. input frequency figure 1-3. linearity figure 1-4. frequency response figure 1-5. cross-talk figure 1-6. fft (1khz, 0dbfs) figure 1-7. fft (1khz, -60dbfs) figure 1-8. fft (noise floor) figure 1-9. fft (out-of-band noise, ~ 130khz) 2. fs=96khz figure 2-1. thd+n vs. input level figure 2-2. thd+n vs. input frequency figure 2-3. linearity figure 2-4. frequency response figure 2-5. fft (1khz, 0dbfs) figure 2-6. fft (1khz, -60dbfs) figure 2-7. fft (noise floor)
asahi kasei [AKD4353] 00/04 - 8 - figure 1-1. thd+n vs. input level figure 1-2. thd+n vs. input frequency akm ak4353 thd+n vs input level (avdd=dvdd=5v, fs=44.1khz, fin=1khz) -110 -90 -109 -108 -107 -106 -105 -104 -103 -102 -101 -100 -99 -98 -97 -96 -95 -94 -93 -92 -91 d b r a -120 +0 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbfs akm ak4353 thd+n vs fin (avdd=dvdd=5v, fs=44.1khz, input level=0dbfs) -100 -80 -99 -98 -97 -96 -95 -94 -93 -92 -91 -90 -89 -88 -87 -86 -85 -84 -83 -82 -81 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz
asahi kasei [AKD4353] 00/04 - 9 - figure 1-3. linearity figure 1-4. frequency response akm ak4353 linearity (avdd=dvdd=5v, fs=44.1khz, fin=1khz) -120 +0 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a -120 +0 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbfs akm ak4353 frequency response (avdd=dvdd=5v, fs=44.1khz, input level=0dbfs) -0.5 +0.5 -0.4 -0.3 -0.2 -0.1 +0 +0.1 +0.2 +0.3 +0.4 d b r a 2k 20k 4k 6k 8k 10k 12k 14k 16k 18k hz
asahi kasei [AKD4353] 00/04 - 10 - figure 1-5. cross-talk figure 1-6. fft (1khz, 0dbfs) akm ak4353 fft (avdd=dvdd=5v, fs=44.1khz, fin=1khz, input level=0dbfs) fft points=16384, avg=8, window=equirriple -160 +0 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz akm ak4353 cross-talk (avdd=dvdd=5v, fs=44.1khz, input level=0dbfs) 20 20k 50 100 200 500 1k 2k 5k 10k hz -120 -100 -119 -118 -117 -116 -115 -114 -113 -112 -111 -110 -109 -108 -107 -106 -105 -104 -103 -102 -101 d b
asahi kasei [AKD4353] 00/04 - 11 - figure 1-7. fft (1khz, -60dbfs) figure 1-8. fft (noise floor) akm ak4353 fft (avdd=dvdd=5v, fs=44.1khz, fin=1khz, input level=-60dbfs) fft points=16384, avg=8, window=equirriple -160 +0 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz akm ak4353 fft (avdd=dvdd=5v, fs=44.1khz, no signal input) fft points=16384, avg=8, window=equirriple -160 +0 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz
asahi kasei [AKD4353] 00/04 - 12 - figure 1-9. fft (out-of-band noise) akm ak4353 fft (outband noise ~130khz; avdd=dvdd=5v, fs=44.1khz, no signal input) fft points=16384, avg=8, window=equirriple -160 +0 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a 600 100k 1k 2k 5k 10k 20k 50k hz
asahi kasei [AKD4353] 00/04 - 13 - figure 2-1. thd+n vs. input level figure 2-2. thd+n vs. input frequency akm ak4353 thd+n vs input level (avdd=dvdd=5v, fs=96khz, fin=1khz) -110 -90 -109 -108 -107 -106 -105 -104 -103 -102 -101 -100 -99 -98 -97 -96 -95 -94 -93 -92 -91 d b r a -120 +0 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbfs akm ak4353 thd+n vs fin (avdd=dvdd=5v, fs=96khz, input level=0dbfs) -100 -80 -99 -98 -97 -96 -95 -94 -93 -92 -91 -90 -89 -88 -87 -86 -85 -84 -83 -82 -81 d b r a 20 40k 50 100 200 500 1k 2k 5k 10k 20k hz
asahi kasei [AKD4353] 00/04 - 14 - figure 1-3. linearity figure 1-4. frequency response akm ak4353 linearity (avdd=dvdd=5v, fs=96khz, fin=1khz) -120 +0 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a -120 +0 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbfs akm ak4353 frequency response (avdd=dvdd=5v, fs=96khz, input level=0dbfs) -0.5 +0.5 -0.4 -0.3 -0.2 -0.1 +0 +0.1 +0.2 +0.3 +0.4 d b r a 2.5k 40k 5k 7.5k 10k 12.5k 15k 17.5k 20k 22.5k 25k 27.5k 30k 32.5k 35k 37.5k hz
asahi kasei [AKD4353] 00/04 - 15 - akm ak4353 fft (avdd=dvdd=5v, fs=96khz, fin=1khz, input level=0dbfs) fft points=16384, avg=8, window=equirriple -160 +0 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a 20 40k 50 100 200 500 1k 2k 5k 10k 20k hz figure 2-5. fft (1khz, 0dbfs) upper: notch off, lower: notch on akm ak4353 fft (avdd=dvdd=5v, fs=96khz, fin=1khz, input level=-60dbfs) fft points=16384, avg=8, window=equirriple -160 +0 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a 20 40k 50 100 200 500 1k 2k 5k 10k 20k hz figure 2-6. fft (1khz, -60dbfs)
asahi kasei [AKD4353] 00/04 - 16 - akm ak4353 fft (avdd=dvdd=5v, fs=96khz, no signal input) fft points=16384, avg=8, window=equirriple -160 +0 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a 20 40k 50 100 200 500 1k 2k 5k 10k 20k hz figure 2-7. fft (noise floor)
asahi kasei [AKD4353 control program] 00/2 - 1 - AKD4353 control program ver 2.0 operation manual 1. connect ibm-at compatible pc with AKD4353 by 10-line type flat cable (packed with AKD4353). take care of the direction of 10pin header (refer to manual of AKD4353). 2. start up windows 95 or windows 98. 3. insert the floppy-disk labeled AKD4353 control program ver 2.0 into the floppy-disk drive. 4. set up ms-dos from start menu. 5. change directory to the floppy-disk drive(ex.a:) at ms-dos prompt. 6. type ak4353. 7. then follow the displayed comment (see the following). ==================== <> ===================== input control mode (3-wire serial or i2c bus) input chip address (2bit) write data/ display register map/ reset etc. loop =========================================================
asahi kasei [AKD4353 control program] 00/2 - 2 - at first the following message is displayed: ****** ak4353 control program ver 2.0 , '00/2 ****** copyright(c) 2000, asahi kasei microsystems co.,ltd. all rights reserved. input control mode 0: 3-wire serial, 1: i2c bus : input 0 or 1. then the following is displayed: input chip address(cad1,cad0) (2 figure, binary) = input chip address in 2 figures of binary. set cad1 and cad0 before the AKD4353 is powered up. when hanging cad1 and cad0, set sw1(-pd) l, then h after that. after chip address is defined, the following default register map is displayed (loop starts from here): 3-wire serial control mode cad1-0=00 ----------------------------------- addr = 00 : 0b ( 0 0 0 0 dif2 dif1 dif0 rstn ) addr = 01 : 01 ( 0 0 dfs1 dfs0 cks2 cks1 cks0 rstn ) addr = 02 : 94 ( pl3 pl2 pl1 pl0 dem1 dem0 atc smute) addr = 03 : ff ( att7 att6 att5 att4 att3 att2 att1 att0 ) addr = 04 : ff ( att7 att6 att5 att4 att3 att2 att1 att0 ) addr = 05 : 00 ( 0 0 0 0 0 0 v txe ) addr = 06 : 00 ( 0 cs29 cs28 cs24 cs3 cs2 cs2 cs1 ) addr = 07 : 04 ( cs15 cs14 cs13 cs12 cs11 cs10 cs9 cs8 ) input 1(write), r(reset), t(table), i(increment), d(decrement) or s(stop) : 1) if you input 1, you can write data to ak4353. you can write data to ak4353 input register address (2 figure, hex) (00-07) = input register address in 2 figures of hexadecimal. then current data of this address is displayed: addr = 00 : 0b ( 0 0 0 0 dif2 dif1 dif0 rstn ) 0 0 0 0 1 0 1 1 input register data (2 figure, hex) (00-ff) = you can write control data to this address. input control data in 2 figures of hexadecimal. refer to datasheet of ak4353. then the data written to this address is displayed: addr = 00 : 09 ( 0 0 0 0 dif2 dif1 dif0 rstn ) 0 0 0 0 1 0 0 1
asahi kasei [AKD4353 control program] 00/2 - 3 - 2) if you input r or r, this program writes default data to all register addresses. 3) if you input t or t, current register map is displayed. 4) if you input i or i, this program increment data of current address by 1 (only for addr=03h or 04h). you can increment att value by 1step. 5) if you input d or d, this program decrement data of current address by 1 (only for addr=03h or 04h). you can decrement att value by 1step. 6) if you input s or s, this program is terminated.
5 5 4 4 3 3 2 2 1 1 d d c c b b a a sck/cclk sda/cdti -cs l h analog g round digital ground 3v avdd sda(ack) for 74lvc541 for 74hcu04, 74ls07, 74hc14, 74ac74, 74hc4040 cad1 cad0 i2c ttl tst m2 m1 m0 ak4353 a AKD4353 a4 12 monday, november 15, 1999 title size document number rev date: sheet of avdd2 dvdd mcki bick sdti mcko lrck aoutl aoutr dzf m1 dvdd m2 m0 dvdd dvdd 5v avdd 3v 5v 5v 5v + c3 47u l1 (short) 1 2 + c11 10u + c10 10u c13 0.1u c17 0.1u + c12 10u r2 5.1 l3 (short) 1 2 d1 sw1 -pd c16 0.1u jp2 5v-3v jp3 dvdd 1 2 3 r10 10k r11 10k r12 10k r15 51 u4d 74ls07 9 8 r13 10k u4a 74ls07 1 2 + c19 10u + c15 10u r6 220 r3 220 r7 27k c6 0.1u u2 74lvc541 2 3 4 5 6 7 8 9 1 19 18 17 16 15 14 13 12 11 a1 a2 a3 a4 a5 a6 a7 a8 g1 g2 y1 y2 y3 y4 y5 y6 y7 y8 + c1 47u c9 0.1u c7 0.1u c8 0.1u jp1 gnd r14 10k sw2 mode 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 rp1 47k 1 2 3 4 5 6 7 8 9 c5 0.1u c4 0.1u r4 27k + c2 47u c20 0.1u r5 10k u3b 74hc14 3 4 u3a 74hc14 1 2 u3c 74hc14 5 6 u3d 74hc14 9 8 u3e 74hc14 11 10 u3f 74hc14 13 12 u4c 74ls07 5 6 u4f 74ls07 13 12 r16 51 jp4 3-wire r17 51 r18 51 port2 ctrl 10 8 6 4 2 1 3 5 7 9 c14 0.1u r1 1k port1 totx174 1 2 3 4 5 6 gnd if vcc in 5 6 l2 10u 1 2 u4b 74ls07 3 4 u4e 74ls07 11 10 r33 (short) r32 (short) r31 (short) r30 (short) r29 (short) u? ak4353 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 mcko tx dvdd dvss mcki bick sdti lrck pdn csn scl/cclk sda/cdti tst ttl i2c cad1 cad0 aoutr aoutl vcom avss avdd nc dzf
5 5 4 4 3 3 2 2 1 1 d d c c b b a a vd gnd rca opt ad/rom sdata mclk lrck bick thr inv xtl bnc dir x2 x1 x1/8 x1/4 x1/2 adc dir dir adc data gnd x4 on off (10k ,10k) (10k ,10k) (10k ,10k) (10k ,10k) x1 x1/128 x1/256 interface a AKD4353 a3 22 monday, nove mber 15, 1999 title size document number rev date: sheet of x_bick dir_lrck lrck bick m0 m2 dir_ bick dir_lrck x_bick m1 sdti dir_bick x_lrck avdd2 dzf aoutl avdd2 aoutr mcko mcki x_lrck 5v 5v 5v vd port4 torx174 1 3 4 2 6 5 out vcc gnd gnd 6 5 c24 0.1u + c22 10u c31 0.01u c28 0.01u jp16 rca/opt 1 2 3 l4 10u 1 2 u7b 74hcu04 3 4 r23 1k port3 adc/rom 1 2 3 4 5 6 7 8 9 10 jp12 dir_data c30 0.1u r26 1k c29 47n r25 1k + c23 10u c25 0.1u c27 (open) r24 1m r28 51 u7c 74hcu04 5 6 j4 bnc u7d 74hcu04 9 8 u7e 74hcu04 11 10 jp15 xte r21 10k jp13 dir 1 2 3 l5 47u 1 2 c26 (open) jp11 sdti 1 2 3 j3 rca x1 11.2896mhz 1 2 u8a 74ac74 2 3 5 6 4 1 d clk q q pr cl r22 1k r27 75 u6 74hc4040 10 11 9 7 6 5 3 2 4 13 12 14 15 1 clk rst q1 q2 q3 q4 q5 q6 q7 q8 q9 q10 q11 q12 u8b 74ac74 12 11 9 8 10 13 d clk q q pr cl jp9 x_mclk jp6 lrck jp7 bick r19 10k tr2 rn2202 1 3 2 jp5 dzf tr1 rn1202 1 3 2 tr3 2sc3327 1 3 2 c21 0.1u j1 aoutl tr5 rn2202 1 3 2 r20 10k tr4 rn1202 1 3 2 j2 aoutr tr6 2sc3327 1 3 2 u7f 74hcu04 13 12 u7a 74hcu04 1 2 jp8 bick_phase 1 2 3 jp14 clk u5 x_bick 1 2 3 4 5 6 7 8 jp10 x_lrck led1 verf 2 1 led2 prem 2 1 u9 cs8414 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 c cd/f1 cc/f0 cb/e2 ca/e1 c0/e0 vd+ dgnd rxp rxn fsync sck cs12/fck u cbl sel m3 m2 mck filt agnd va+ m0 m1 erf sdata ce/f2 verf
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